1. Field of the Invention
The present invention relates to a remaining film thickness distribution estimating method for estimating the thickness of film remaining on each activation region (remaining film thickness) after chemical mechanical polishing (CMP) step in, for example, an STI-CMP step, a patterning mask design method using the method for estimating remaining film thickness distribution, and a method for manufacturing semiconductor devices by using a patterning mask designed by the aforesaid patterning mask design method.
2. Description of the Related Art
With the recent increasing trend toward higher integration of semiconductor devices, device isolation technologies for insulatively isolating adjacent semiconductor devices are being extensively used. Among the device isolation technologies, the trench isolation method for insulatively separating semiconductor devices by an insulating film filling a device isolation groove or trench is effective, because it permits reduced separating width to be achieved.
The trench isolation method generally includes an STI-CMP step that stands for shallow trench isolation based on chemical mechanical polishing.
According to the trench isolation method, etching is first carried out by using a patterning mask to form a trench in a semiconductor substrate. At this time, the region excluding the trench provides an activation region (hereinafter referred to also as “active region”).
Thereafter, an insulating film is formed over the active region to fill the trench by high density plasma (HDP) chemical vapor deposition (CVD), then CMP is carried out on the semiconductor substrate to form shallow trench isolation portion thereon.
If, however, the semiconductor substrate is etched using the patterning mask to have mixture of an area with sparse active regions formed therein (a sparse active region) and an area with dense active regions formed therein (a dense active region), then a difference in remaining film thickness of the surface protection film remaining on active regions results between the sparse and dense regions after the CMP step. The difference is referred to as “global difference”.
The global difference occurs due to the elastic deformation of a polishing pad or abrasive cloth brought in contact with the surface of an insulating film through the intermediary of slurry during the CMP step, the elastic deformation being attributable to an uneven density of the active regions.
In a sparse active region, the polishing pressure applied by the polishing pad to a semiconductor substrate is markedly influenced by the flatness of the surface of the substrate. In a dense active region, the polishing pressure applied by the polishing pad to the semiconductor substrate is scattered by unevenness of the surface. Thus, the difference in polishing pressure takes place between sparse active regions and dense active regions.
As a result, the polishing rate or speed in the dense active regions is slower than the polishing rate in the sparse active regions. Furthermore, the polishing is performed at a time in the CMP step, so that imbalance in remaining film between the sparse and dense active regions, that is, the occurrence of a global difference, is unavoidable.
Especially if the global difference is too large to be ignored, then the active region itself of a sparse active region is cut, whereas an insulating film still remains on the active region of a dense active region when the CMP step is completed. This leads to significantly deteriorated product yield or reliability.
Conventionally, a pseudo active region has been formed on the entire surface of a semiconductor substrate, as necessary, to make adjustment or the like of polishing rate for sparse and dense active regions. It has been, however, difficult to effectively control a global difference.
Thus, there has been demand for a solution that controls the undesirable global difference and permits improved global flatness.